Towards a Formal Semantics of Verilog Using Duration Calculus

1 I n t r o d u c t i o n Modern hardware design typically uses hardware description languages to express designs at various levels of abstraction. A hardware description language is a high level programming language, with the usual programming constructs such as assignments, conditionals and iterations, and appropriate extensions for real-time, concurrency and data structures suitable for modelling hardware. The common approach is to first build a high level design using programming constructs. The high level design is then recoded using a subset of the description language which is closer to implementation. This process may be repeated several times until the design is at a sufficiently lower level such that the hardware can be synthesised from it. For ensuring correctness of the development, precise understanding of the description language used is apparently important. Verilog is a hardware description language widely used in industry, but its s tandard semantics [7] is informal. A formal semantics will also be the basis of further formal support for the language. This includes methods to prove that the highest level description satisfies the overall requirements and that a lower level description correctly implements a higher level one. Verilog programs can exhibit a rich variety of computations, when several features of the language are intertwined. The features include * On leave from Catholic University of Pelotas, Cx.Postal 402 (96010-000), Pelotas-RS, Brazil. Email: gerardo~atlas.vcpel.tche.br